Training & Live Sessions on

Analog
Layout

Be that Analog Layout Designer with the world-class industry-oriented training program using the Cadence Virtuoso tool.

2000+ Engineers trainers provided to Industry!

Course Details

Exam Syllabus

Need to qualify for the screening test and technical interview. The test would be conducted in Basic Electronics – R, L, C, Diode, BJT, FET, CMOS, etc. Analog basic circuits Like RLC circuits, Amplifiers, Opamp, Oscillators, and Network Theory. Digital Electronics – Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits, and Counters.

Qualification

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.

Academics

Aggregate of 65% & Above

No. of Seats

Fee

₹80,000/- [+18% GST]

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Chandra Rao Kondepati

Mr. Chandra is the Analog Layout Manager in MosChip leading a team of 50 members, and he has been working in the VLSI industry for the last 18 years.

Sarath Chandra

Mr. Sarath Chandra is the Analog Layout faculty with more than 11+ years of Industry experience...

Course Content

Fundamental concepts in MOSFET, Second order effects, Digital logic gates design, Fabrication concepts, Latch-Up, Antenna effect, and Standard cell layout.

Fundamentals of analog circuits like Amplifiers, Opamps, Differential amplifiers, BGR, DAC, and PLL. Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD, and STI effects, ESD concepts, and Layout guidelines. Physical verification concepts like LVS, DRC, and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks, ESD path checks, Chip level issues, and FINFET fundamentals. The trainees get to work on 4 to 5 different designs. The assignments are designed in such a way that our trainees have a clear understanding of developing layouts from schematics following the design constraints, process challenges, and layout guidelines and verified their designs and extracted within the given specification limits.