Design Verification

Basics of RC circuits; Charging and discharging; governing equations and their explanation; rise time and fall time, RC time constant, Elmore delay model in distributed RC network; concept of drive strength, contention, tri-state and noise margin. Practice problems.

Binary Number systems: Sign-magnitude (SM),  1’s complement, 2’s complement(TC);  addition of 2’complement numbers, Logical and arithmetic shifting, sign extension, binary fractions; Practice problems in logic circuits related to binary number systems.

Combinational circuits: Karnaugh map, De-Morgan’s theorems, Multiplexer as a universal element, de-multiplexers, using multiplexers for constructing other logic gates – N/AND, N/OR, XOR, XNOR, NOT, Buffer.   Practice problems in combinational logic

Working of NMOS FET from first principles. Concept of threshold voltage;  cutoff region, linear regin and saturation region. Transmission of an imperfect 1/0 and perfect 1/0; Building logic gates using MOS transistors as transmission switches. Construction of 2-i/p NAND, NOR, AND, OR gates, and inverter. Voltage transfer characteristic (VTC) of an inverter.

More combinational circuits: Arithmetic comparator for 4 bits, cascaded arithmetic comparators, demultiplexers, decoders, priority encoders, extended Priority encoders, 2-input hardware sorter, 4-input sorter, seven segment decoder implementation, carry lookahead adder, carry save adder, multiplier, Booth’s  multiplier; Practice problems in Combinational logic.

Sequential Logic: Basic difference between sequential and combinational. Construction of a 1-bit latch using transmission and feedback CMOS switches.  Construction of an edge triggered flipflop using latches. Difference between the operation of a latch and the operation of a flip flop. Introduction to FSM. Timing parameters in sequential elements – setup time, hold time and clk-to-Q propagation delay. Clock skew. Practice problems

Different types of flipflops. D, JK and T flip flop; Characteristic table and excitation tables, converting from one type of FF to another; Timing parameters of flip flops and Concept of metastability; Timing violations; Clock Domain Crossing (CDC); single-bit 2-FF synchronizer.

General representation of a Finite State Machine (FSM); Moore and Mealy State machines; Shift registers, Counters; counters used as frequency dividers, Sequence detector, design of a divide-by-5 counter with 50% duty cycle.

Problem solving in FSM: Washing machine controller, Candy vending machine controller, Traffic signal controller, Round robin arbiter, etc. Problems in frequency division using counters and how to get an output frequency with a certain division ratio and duty cycle.

Introduction to STA: different types of timing paths; False path and multicycle path. Clock skew; max permissible clock skey in a circuit and how to overcome hold timing violation and setup timing violations in circuits; Useful skew and max frequency of operation.

Verilog HDL: Introduction, Data Types, Verilog operators, different levels of modelling, behavioral modeling, always vs initial blocks, blocking vs nonblocking assignments, Stratified event queue, tasks and functions, recursive tasks and functions, compiler directives, system functions, Writing the design code for the problems done; writing test benches in Verilog.

System Verilog: New data types, processes, fundamentals of OOP, transaction class, generator class, interface and modports, driver class, environment class, scoreboard class etc. Porting the Washing machine controller test bench and candy vending machine controller testbench to SV.