Design Verification
Help the world by becoming a World-class Design Verification Engineer. The world-class industry-oriented VLSI – Design Verification training using Cadence & Mentor Graphic tool.
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Course Details
Need to qualify for the screening test and technical interview. The test would be conducted in Basic Electronics – BJT, FET, CMOS; Digital Electronics – Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits, Counters, C-Programming, and Aptitude.
B.Tech – ECE/EEE | 2021 to 2025 Pass-out | Minimum 65%
M.Tech – ECE/EEE | 2023 to 2025 Pass-out | Minimum 65%
Aggregate of 65% & Above
80
₹95,000/- [+ 18% GST].
Kishore Vennela
- 6 Months of practical learning
- Hands-on experience with Tools
- Placement Assistance
- Certificate of Completion
Course Content
Digital Logic :
Introduction to Digital Systems and Number system, Logic gates and Conversions, Min and Max Terms, K-Maps,
Combinational logic: Alternate designs in Combinational circuits, Dataflow Model: Mux design and code, higher order mux using instantiation, encoders and priority encoders, dual and triple priority encoders design,
Sequential circuits : FF Modeling from the inverter blocks, FF Operation and characteristic table and conversions, D-FF Waveform analysis, (D-FF based) Analysis and waveform representation, Shift Registers Operation (SISO,SIPO,PIPO), classification, and Usage, USR design aspect, modes of operation. FIFO: Functionality and Synchronous FIFO Verilog code and logic aspects
Counters: Design of 3-bit Synchronous Counters using D,T and JK -FLIPFLOPS, MOD Counter Design, individual FF outputs as clock values, Custom clock generation,
FSM’s: FSM: Mealy and Moore Hardware Perception, Truth Table to FSM, FSM as Circuit. FSM Modeling for sequence Detector, Set-up and Hold-Times in Sequential circuits, Delays, Task and Function,
Verilog for Verification : Task and Functions, fork-join.
Weekly Assignments
System Verilog:
Introduction: Verilog vs SV, Datatypes : 2-state and 4-state, typedef, enum, Loops: for forever, while dowhile and foreach, Arrays: Packed Unpacked with examples. Dynamic Array with examples, Associative Array with examples, Queues with examples, Classes and methods: Introduction: Objects, Class instances, inheritance, polymorphism, Inheritance with examples: Object handle assignments and $cast, Super construct and application, multilevel inheritance, static variables, static functions and usage. Polymorphism: virtual method and its significance, Randomization and Constraints.
Inter Process Communication: fork-join/join_any/join_none, semaphore and events with examples, interface and virtual and pure virtual interface, clocking blocks, System Verilog environment for verification, Creation for D-FF and a Mux, Assertions, Assertions with Binding. Interface and virtual and pure virtual interface, Clocking blocks. SV Environment Topology Creation and Execution.
Weekly Assignments
Projects:
Project Work-1: SV Environment for Updown Counter with Coverage and Assertions
Project Work-2: SV Environment for AMBA APB-3 Protocol
Verilog:
Abstraction Levels in Verilog : Port connection rules, Lexical Conversion, Gate level Abstraction,
Dataflow model : Operators, Adders, comparators and Code Converters, Mux design and code, higher order mux using instantiation, encoders and priority encoders, dual and triple priority encoders design in Verilog.
Behavioral Abstraction in Verilog and Verilog Parameters, Blocking and Non-Blocking, Harware Interpretation, Control Constructs: if, else-if, case: case,casez and casex with illustration and usage in Verilog, Example based explanation and hardware level interpretation of if, if-else and case statements. Introduction to Stratfied Event Queue
Loop constructs: forever, repeat, while and for loops. Example of LFSR using for loop
Sequential Circuit Analysis: Example, Shift Registers(SISO,SIPO,PIPO) Verilog Code, Verilog code in Huffman Style coding, Verilog Programming: Counters Verilog implementations and Test bench writing
Weekly Assignments
Projects:
Verilog Based Design Project Work with Verification: Project-1: Custom ALU
Verilog BaSed Design Project Work with Self Check Project-2: Custom UpDown Counter
Universal Verification Methodology(UVM)
UVM Basics, Factory Registrations and UVM Phases, Sequence to driver communication Ports and Usage, Config_db and Config Class, ,UVM Reporting Mechanism, Nested Sequences, Virtual Sequence, Virtual Sequence and Virtual Sequencer, Discussion on Nested, Virtual sequence and Virtual Sequencer Concepts, Stimulus Modeling
Project Work-1: UVM Environment for AMBA APB-3 Protocol
Project Work-2: APB Based Ethernet Protocol with Coverage and Assertions
Project Work-3: RAL Based Ethernet Protocol Verification
Perl Scripting
Variable and Arrays, File handling, Perl for Automation, Topology Code building, Customizable Environment Creation Code Building.
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