Be that Physical Designer with the world-class industry-oriented VLSI – Physical Design training program using the Cadence Encounter tool.
2000+ Engineers trainers provided to Industry!
You need to qualify the screening test and technical interview. The test would be conducted in Basic Electronics – BJT, FET, CMOS; Digital Electronics – Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits, and Counters. (All are subjective type questions)
B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics.
Aggregate of 65% & Above
₹1,50,000/- [+ 18% GST].
Srinivasa Kakumanu (KS)
Fundamental concepts in Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floor planning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that trainees have a clear understanding about handling the design from Synthesis to Sign-off within the given specification limits of Area, Timing and Power.
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