Experience: 26+ years
Educational Qualification: B.Tech from OU
KS was the CEO of the Institute of Silicon Systems. He has been in the VLSI industry for the last 26 years and he worked as General Manager, ASIC Design (India), Infotech Enterprises Ltd until the end of last year. Mr. KS led/managed 70+ ASICs all the way from 0.14um to 40nm – working at QualCore, TTM (and later Infotech – Infotech acquired TTM in Sept 2008), and Ikanos. He was in the US between 2000-2007, and managed teams at TTM inc., and Ikanos. Mr. KS quit Infotech in Nov 2010 and he has been training students at MosChip Institute of Silicon Systems Private Ltd (M-ISS) in Madhapur, Hyderabad since then.
Mrs. Sarala Beenedi
Experience: 32+ years
Educational Qualification: M.Tech from JNTU
Sarala Beeneedi is the Technical Director of the Institute of Silicon Systems. She has over 32 years of industry experience spanning FPGA (Xilinx FPGAs) design, ASIC design, Digital Design, and Hardware design. She was in the USA from 2001 to 2005 and worked for a Physical Design services company (Time To Market Inc) as Senior ASIC Designer. She was Vice President of the FPGA group at Taray Technologies India Pvt Ltd and made a significant contribution to the growth of the company. She has extensive hands-on experience and played a key role for the last ten years being in a managerial position.
Mr. Kattekola Naresh
Experience: 10+ years
Educational Qualification: Ph.D. from NIT Meghalaya (Pur)
Kattekola Naresh has obtained his B.Tech degree from Jyothishmathi Institute of Technology & Science, Karimnagar, and a Master’s degree from CVR Engineering College, Hyderabad. He is currently pursuing Ph.D. from NIT Meghalaya, Shillong. He has 10 years of teaching experience. He published papers on Low Power VLSI applications. His area of interest is Low Power techniques, Low Power VLSI Design, FPGA Implementation, Arithmetic Circuits, and Approximate Computing.
Mr. Subbarao Y. K.
Experience: 15+ years
Educational Qualification: M.Tech (Electronics-VLSI)
Subbarao currently working as a Senior Verification Engineer. He has been in the VLSI industry for 5+ years and teaching for 10+ years of experience. Expertise in Verification language, such as Verilog, System Verilog, and UVM. He is working as a verification engineer on various real-time projects.
Mr. Chandrarao Kondepati
Experience: 18+ years
Educational Qualification: M.Tech (Electronics-VLSI)
Mr. Chandra Rao is currently working as an senior analog layout manager in MosChip, leading a team of 50 members, and he has been working in the VLSI industry for the last 18 years. His expertise is in analog layout design for Power management circuits, PLL, DLL, Data Converter circuits, and SerDes. He has worked on multiple Test and Product chips all the way from 500nm to 5nm.
Prior to MosChip, He has been in the Analog Layout in different roles in various companies like Infotech, and Qualcore logic limited until 2011.
Mr. Sunil Kumar Noule
Experience: 13+ years
Educational Qualification: B.Tech from JNTU
Sunil currently working as a Corporate Trainer in M-ISS. He has 13+ years of Industrial experience in various domains, 9+ years of experience as a developer and a trainer in Embedded systems & 4 years of experience as an NPI & Process engineer in the Electronics Manufacturing Industry. He worked as a System Design Engineer in NVIDIA on various Tegra processors, FFDs, and on different Platforms (Smart Phones, Tablets & Gaming Portables).