Experience: 26+ Years
Educational Qualification: B.Tech from OU
KS was the CEO of the Institute of Silicon Systems. He has been in the VLSI industry for the last 26 years and he worked as General Manager, ASIC Design (India), Infotech Enterprises Ltd until the end of last year. Mr. KS led/managed 70+ ASICs all the way from 0.14um to 40nm – working at QualCore, TTM (and later Infotech – Infotech acquired TTM in Sept 2008), and Ikanos. He was in the US between 2000-2007, and managed teams at TTM inc., and Ikanos. Mr. KS quit Infotech in Nov 2010 and he has been training students at MosChip Institute of Silicon Systems Private Ltd (M-ISS) in Madhapur, Hyderabad since then.
Mrs. Sarala Beenedi
Experience: 32+ Years
Educational Qualification: M.Tech from JNTU
Sarala Beeneedi is the Technical Director of the Institute of Silicon Systems. She has over 32 years of industry experience spanning FPGA (Xilinx FPGAs) design, ASIC design, Digital Design, and Hardware design. She was in the USA from 2001 to 2005 and worked for a Physical Design services company (Time To Market Inc) as Senior ASIC Designer. She was Vice President of the FPGA group at Taray Technologies India Pvt Ltd and made a significant contribution to the growth of the company. She has extensive hands-on experience and played a key role for the last ten years being in a managerial position.
Mr. Anand Shankar Moghe
Experience: 35+ Years
Educational Qualification: Masters degree in ECE from the Philips International Institute in Netherlands
For the past few years Anand S Moghe was into training graduate engineers in VLSI so as to impart specific skills required to make them employable. He spent about 18 months working in a project under the DDUGKY scheme of Government of India, training graduate engineers who come with a rural background. A majority of these engineers are now employed with several reputed organizations across India.
Anand Moghe was a Senior Engineering Manager in Xilinx India at Hyderabad, at the time of his retirement from the industry in 2014. Prior to that he worked in senior management positions in companies like Cypress Semiconductors in Bangalore, and Mentor Graphics, Qualcore Logic and CMC – all in Hyderabad. He has also worked as Head of ASIC Design and Verification services in eInfochips, an Ahmedabad based company. Although his domain of experience has been microprocessor-based board level design and front-end VLSI digital design and IP (Intellectual Property) development, he has worked in an EDA tool company, semiconductor product companies and VLSI services organizations. He also had a stint in ECIL for 5 years, working in the area of RF transmitters and receivers for a defense project.
Anand Moghe was a visiting faculty at the Hyderabad campus of BITS, Pilani, where he taught Digital Signal Processing to M. Tech students. He has also delivered corporate training in Verilog at Semiconductor product companies like Sandisk and Maxim – both in Bangalore. He has lectured on DFT (Design for Testability) at VEDA IIT in Hyderabad for many years, and has also delivered technical lectures at conferences and seminars in India and abroad.
He obtained his Masters degree in Electronics and Communication Engineering from the Philips International Institute in Netherlands in 1983 and his Bachelors in (Electronics and Communication) Engineering from Osmania University in 1975.
Mr. Subbarao Y. K.
Experience: 15+ Years
Educational Qualification: M.Tech (Electronics-VLSI)
Subbarao currently working as a Senior Verification Engineer. He has been in the VLSI industry for 5+ years and teaching for 10+ years of experience. Expertise in Verification language, such as Verilog, System Verilog, and UVM. He is working as a verification engineer on various real-time projects.
Mr. Chandrarao Kondepati
Experience: 18+ Years
Educational Qualification: M.Tech (Electronics-VLSI)
Mr. Chandra Rao is currently working as an senior analog layout manager in MosChip, leading a team of 50 members, and he has been working in the VLSI industry for the last 18 years. His expertise is in analog layout design for Power management circuits, PLL, DLL, Data Converter circuits, and SerDes. He has worked on multiple Test and Product chips all the way from 500nm to 5nm.
Prior to MosChip, He has been in the Analog Layout in different roles in various companies like Infotech, and Qualcore logic limited until 2011.
Mr. Anil Kumar Nelgi
Experience: 17+ Years
Educational Qualification: BE (EEE) from University College of Eng., Osmania University, Hyderabad
Anil Kumar is an Embedded Engineering Manager at MosChip with 17 years of experience, including 8 years working on Qualcomm platforms. He has experience in analysis, design, development, integration, and implementation of various applications on different platforms like Embedded, Brew Platform, Android, and Linux. He has good knowledge of C, C++, and Assembly language programming, and multimedia, Android Operating Systems, and different processor architectures. Anil has worked on projects involving integrating glue frameworks, porting driver stacks, developing standalone applications, and development of interface layers of different OEMs to support new features on Audio, Display, and Image related use cases. He is also proficient in working with tools such as Jira, Perforce, Clear case, Git, and Gerrit. Anil has experience in leading teams, mentoring engineers on embedded concepts, and system programming.
Mr. Kishore Vennela
Experience: 12+ Years
Educational Qualification: Ph.D. in VLSI Architectures for Robot Control Systems (Pur)
Kishore Vennela holding a M.Tech Degree from JNTU, Hyderabad and pursuing Ph.D in the domain of VLSI Architectures for Robot Control Systems. He has 12+ years of teaching experience and published research articles on Indoor Robot Application with optimum sensing system. He has good experience in hardware level developments on Zynq-7 and Artix-7 series FPGA’s. He is currently working as Corporate trainer for Design Verification in the M-ISS. His area of interest includes Automated Robotic Systems, Optimum VLSI Architectures, and Realtime Verification of FPGA Design Models.
Mr. Sarath Chandra
Experience: 11+ Years of Research and Corporate Training Experience.
Educational Qualification: Ph.D. in VLSI on FINFET SRAM (Pur)
Mr. K Sarath Chandra is currently working as corporate trainer for Analog layout in the M-ISS. He has 11+ years of teaching and research experience. He published research articles on Comparator, ADC design and FINFET SRAM. He completed his masters from VIT university, Vellore and pursuing Ph.D. in the domain of VLSI on Low power FINFET SRAM Design. His expertise is in Analog IC Design and Layout, Low Power techniques, and Low Power VLSI Design. He completed two research projects in the area of VLSI domain, one consultancy project of Ananth technologies and AICTE funded project titled “Development of Low Power and High-Speed FPGA based IP Core Mini Ace Architecture Compatible to Data Device Corporation”.
Mr. Kattekola Naresh
Experience: 10+ Years
Educational Qualification: Ph.D. from NIT Meghalaya (Pur)
Kattekola Naresh has obtained his B.Tech degree from Jyothishmathi Institute of Technology & Science, Karimnagar, and a Master’s degree from CVR Engineering College, Hyderabad. He is currently pursuing Ph.D. from NIT Meghalaya, Shillong. He has 10 years of teaching experience. He published papers on Low Power VLSI applications. His area of interest is Low Power techniques, Low Power VLSI Design, FPGA Implementation, Arithmetic Circuits, and Approximate Computing.